This invention relates to integrated circuits and more particularly it relates to such circuits which include provisions for noise immunity.
In any integrated circuit, various input signals are sent through input pads to the circuit. There, the circuit processes the input signals and generates output signals which are sent off of the circuit through output pads. However, each of the output pads has associated with it a small but non zero parasitic inductance; and thus a noise spike is generated in the circuit when the magnitude of the current through the output pads switches.
This noise spike is then parasitically coupled to other parts of the circuit where no switching is supposed to occur. That is, various parasitic capacitances and resistances in the circuit will couple the noise on the output pads to other portions of the circuit, and there the noise can cause a problem. For example, if the noise is coupled to the base of a transistor which drives an output pad and which is not supposed to be switching (e.g., a quiet driver), then that quiet driver will respond to the noise on its base by generating an even larger current noise spike on its output due to the large .beta. of the transistor. This in turn can cause errors in the system in which the integrated circuit is used.
In the prior art, one way of coping with switching noise was to construct the output drivers such that they switched at a relatively slow speed. In other words, the speed at which the output drivers operated was intentionally slowed down. This in turn reduced the magnitude of noise that was generated on the output pads since that noise is proportional to the parasitic inductance of the pins times and magnitude of the current that switches divided by the time interval in which the current switches. However, this solution is undesirable because it severely limits the maximum speed at which the circuitry operates.
Accordingly, a primary object of the invention is to provide an integrated circuit having improved noise immunity.
Another object of the invention is to provide an integrated circuit having high noise immunity plus high switching speeds.